[PATCH v2 1/3] drm/exynos/decon5433: add dynamic zpos support

[Andrzej Hajda]

DECON has fixed hardware window order. To implement dynamic zpos
normalized_zpos of active plane has to be connected to window number, and
remaining windows have to be disabled.

v2: fixed pixel format setting

Signed-off-by: Andrzej Hajda <***@samsung.com>
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 45 ++++++++-----------
1 file changed, 19 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 5b4e0e8b23bc..bdfec5f977e9 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -83,14 +83,6 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
[CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
};

-static const unsigned int capabilities[WINDOWS_NR] = {
- 0,
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
-};
-
static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
u32 val)
{
@@ -314,12 +306,13 @@ static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
}
}

-static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
- struct drm_framebuffer *fb)
+static void decon_win_set_pixfmt(struct decon_context *ctx,
+ struct exynos_drm_plane *plane)
{
- struct exynos_drm_plane plane = ctx->planes[win];
struct exynos_drm_plane_state *state =
- to_exynos_plane_state(plane.base.state);
+ to_exynos_plane_state(plane->base.state);
+ unsigned int win = state->base.normalized_zpos + ctx->first_win;
+ struct drm_framebuffer *fb = state->base.fb;
unsigned int alpha = state->base.alpha;
unsigned int pixel_alpha;
unsigned long val;
@@ -402,7 +395,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
to_exynos_plane_state(plane->base.state);
struct decon_context *ctx = crtc->ctx;
struct drm_framebuffer *fb = state->base.fb;
- unsigned int win = plane->index;
+ unsigned int win = state->base.normalized_zpos + ctx->first_win;
unsigned int cpp = fb->format->cpp[0];
unsigned int pitch = fb->pitches[0];
dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
@@ -446,25 +439,24 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
| BIT_VAL(state->crtc.w * cpp, 14, 0);
writel(val, ctx->addr + DECON_VIDW0xADD2(win));

- decon_win_set_pixfmt(ctx, win, fb);
+ decon_win_set_pixfmt(ctx, plane);

/* window enable */
decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
}

-static void decon_disable_plane(struct exynos_drm_crtc *crtc,
- struct exynos_drm_plane *plane)
-{
- struct decon_context *ctx = crtc->ctx;
- unsigned int win = plane->index;
-
- decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
-}
-
static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
{
struct decon_context *ctx = crtc->ctx;
unsigned long flags;
+ int win = hweight32(crtc->base.state->plane_mask) + ctx->first_win;
+
+ /* disable windows corresponding to disabled planes */
+ for (; win < WINDOWS_NR; ++win) {
+ if (!readl(ctx->addr + DECON_WINCONx(win)) & WINCONx_ENWIN_F)
+ break;
+ decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
+ }

spin_lock_irqsave(&ctx->vblank_lock, flags);

@@ -538,7 +530,7 @@ static void decon_disable(struct exynos_drm_crtc *crtc)
* a destroyed buffer later.
*/
for (i = ctx->first_win; i < WINDOWS_NR; i++)
- decon_disable_plane(crtc, &ctx->planes[i]);
+ decon_set_bits(ctx, DECON_WINCONx(i), WINCONx_ENWIN_F, 0);

decon_swreset(ctx);

@@ -607,7 +599,6 @@ static const struct exynos_drm_crtc_ops decon_crtc_ops = {
.disable_vblank = decon_disable_vblank,
.atomic_begin = decon_atomic_begin,
.update_plane = decon_update_plane,
- .disable_plane = decon_disable_plane,
.mode_valid = decon_mode_valid,
.atomic_flush = decon_atomic_flush,
};
@@ -628,7 +619,9 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
ctx->configs[win].zpos = win - ctx->first_win;
ctx->configs[win].type = decon_win_types[win];
- ctx->configs[win].capabilities = capabilities[win];
+ ctx->configs[win].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS
+ | EXYNOS_DRM_PLANE_CAP_WIN_BLEND
+ | EXYNOS_DRM_PLANE_CAP_PIX_BLEND;

ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
&ctx->configs[win]);

[Andrzej Hajda]

Hardware window disabling is performed in multiple places. Creating
helper for it simplifies the code and prepares it for further improvements.

Signed-off-by: Andrzej Hajda <***@samsung.com>
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 786a8ee6f10f..a7993f5d8371 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -345,6 +345,14 @@ static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
writel(val, ctx->regs + SHADOWCON);
}

+static void fimd_disable_win(struct fimd_context *ctx, int win)
+{
+ fimd_enable_video_output(ctx, win, false);
+
+ if (ctx->driver_data->has_shadowcon)
+ fimd_enable_shadow_channel_path(ctx, win, false);
+}
+
static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
{
struct fimd_context *ctx = crtc->ctx;
@@ -363,12 +371,7 @@ static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
u32 val = readl(ctx->regs + WINCON(win));

if (val & WINCONx_ENWIN) {
- fimd_enable_video_output(ctx, win, false);
-
- if (ctx->driver_data->has_shadowcon)
- fimd_enable_shadow_channel_path(ctx, win,
- false);
-
+ fimd_disable_win(ctx, win);
ch_enabled = 1;
}
}
@@ -880,15 +883,11 @@ static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
struct exynos_drm_plane *plane)
{
struct fimd_context *ctx = crtc->ctx;
- unsigned int win = plane->index;

if (ctx->suspended)
return;

- fimd_enable_video_output(ctx, win, false);
-
- if (ctx->driver_data->has_shadowcon)
- fimd_enable_shadow_channel_path(ctx, win, false);
+ fimd_disable_win(ctx, plane->index);
}

static void fimd_enable(struct exynos_drm_crtc *crtc)
@@ -923,7 +922,7 @@ static void fimd_disable(struct exynos_drm_crtc *crtc)
* a destroyed buffer later.
*/
for (i = 0; i < WINDOWS_NR; i++)
- fimd_disable_plane(crtc, &ctx->planes[i]);
+ fimd_disable_win(ctx, i);

fimd_enable_vblank(crtc);
fimd_wait_for_vblank(crtc);

[Andrzej Hajda]

FIMD has fixed hardware window order. To implement dynamic zpos
normalized_zpos of active plane has to be connected to window number, and
remaining windows have to be disabled.

v2: fixed pixel format setting

Signed-off-by: Andrzej Hajda <***@samsung.com>
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 46 ++++++++++--------------
1 file changed, 18 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index a7993f5d8371..46588a14f0c3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -228,14 +228,6 @@ static const uint32_t fimd_formats[] = {
DRM_FORMAT_ARGB8888,
};

-static const unsigned int capabilities[WINDOWS_NR] = {
- 0,
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
- EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
-};
-
static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
u32 val)
{
@@ -636,12 +628,13 @@ static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
BLENDCON_NEW_8BIT_ALPHA_VALUE);
}

-static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
- struct drm_framebuffer *fb, int width)
+static void fimd_win_set_pixfmt(struct fimd_context *ctx,
+ struct exynos_drm_plane *plane)
{
- struct exynos_drm_plane plane = ctx->planes[win];
struct exynos_drm_plane_state *state =
- to_exynos_plane_state(plane.base.state);
+ to_exynos_plane_state(plane->base.state);
+ unsigned int win = state->base.normalized_zpos;
+ struct drm_framebuffer *fb = state->base.fb;
uint32_t pixel_format = fb->format->format;
unsigned int alpha = state->base.alpha;
u32 val = WINCONx_ENWIN;
@@ -698,7 +691,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
* still better to change dma-burst than displaying garbage.
*/

- if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
+ if (state->src.w < MIN_FB_WIDTH_FOR_16WORD_BURST) {
val &= ~WINCONx_BURSTLEN_MASK;
val |= WINCONx_BURSTLEN_4WORD;
}
@@ -781,6 +774,12 @@ static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
if (ctx->suspended)
return;

+ for (i = hweight32(crtc->base.state->plane_mask); i < WINDOWS_NR; i++) {
+ if (!(readl(ctx->regs + WINCON(i)) & WINCONx_ENWIN))
+ break;
+ fimd_disable_win(ctx, i);
+ }
+
for (i = 0; i < WINDOWS_NR; i++)
fimd_shadow_protect_win(ctx, i, false);

@@ -797,7 +796,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc,
dma_addr_t dma_addr;
unsigned long val, size, offset;
unsigned int last_x, last_y, buf_offsize, line_size;
- unsigned int win = plane->index;
+ unsigned int win = state->base.normalized_zpos;
unsigned int cpp = fb->format->cpp[0];
unsigned int pitch = fb->pitches[0];

@@ -864,7 +863,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc,
DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
}

- fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
+ fimd_win_set_pixfmt(ctx, plane);

/* hardware window 0 doesn't support color key. */
if (win != 0)
@@ -879,17 +878,6 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc,
atomic_set(&ctx->win_updated, 1);
}

-static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
- struct exynos_drm_plane *plane)
-{
- struct fimd_context *ctx = crtc->ctx;
-
- if (ctx->suspended)
- return;
-
- fimd_disable_win(ctx, plane->index);
-}
-
static void fimd_enable(struct exynos_drm_crtc *crtc)
{
struct fimd_context *ctx = crtc->ctx;
@@ -1008,7 +996,6 @@ static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
.disable_vblank = fimd_disable_vblank,
.atomic_begin = fimd_atomic_begin,
.update_plane = fimd_update_plane,
- .disable_plane = fimd_disable_plane,
.atomic_flush = fimd_atomic_flush,
.atomic_check = fimd_atomic_check,
.te_handler = fimd_te_handler,
@@ -1062,7 +1049,10 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
ctx->configs[i].zpos = i;
ctx->configs[i].type = fimd_win_types[i];
- ctx->configs[i].capabilities = capabilities[i];
+ ctx->configs[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS
+ | EXYNOS_DRM_PLANE_CAP_WIN_BLEND
+ | EXYNOS_DRM_PLANE_CAP_PIX_BLEND;
+
ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
&ctx->configs[i]);
if (ret)